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1 of 18 rev: 080805 general description the ds1673 portable system controller is a circuit that incorporates many of the functions necessary for low-power portable products integrated into one chip. the device provides a real-time clock (rtc), nv ram controller, microprocessor monitor, and a 3-channel, 8-bit analog-to-digital converter (adc). communication with the ds1673 is established through a simple 3-wire interface. the rtc provides seconds, minutes, hours, day, date, month, and year information with leap year compensation. the rtc also provides an alarm interrupt. this interrupt works when the ds1673 is powered by the system power supply or when in battery-backup operation, so the alarm can be used to wake up a system that is powered down. automatic backup and write protection of an external sram is provided through the v cco , ceol , and ceoh pins. the backup energy source used to power the rtc is also used to retain ram data in the absence of v cc through the v cco pin. the chip- enable outputs to ram ( ceol and ceoh ) are controlled during power transients to prevent data corruption. ordering information part* voltage (v) pin- package top mark? ds1673e-3 3.0 20 tssop ds1673-3 ds1673e-3+ 3.0 20 tssop ds1673-3 ds1673e-5 5.0 20 tssop ds1673-5 ds1673e-3/ t&r 3.0 20 tssop ds1673-3 ds1673e-3+ t&r 3.0 20 tssop ds1673-3 ds1673e-5/ t&r 5.0 20 tssop ds1673-5 ds1673s-3 3.0 20 so ds1673s-3 ds1673s-5 5.0 20 so ds1673s-5 * all devices are specified over t he 0c to +70c operating range. ? a ??+? anywhere on the top mark denotes a lead-free device. + denotes a lead(pb)-free/rohs-compliant device. features ? provides real-time clock counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap year compensation valid up to 2100 power-control circuitry supports system power-on from day/time alarm ? microprocessor monitor halts microprocessor during power fail automatically restarts microprocessor after power failure monitors pushbutton for external override halts and resets an out-of-control microprocessor ? nv ram control automatic battery backup and write protection to external sram ? 3-channel, 8-bit adc ? simple 3-wire interface ? +3.0v or +5.0v operation pin configuration ds1673 portable system controlle r www.maxim-ic.com 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 s t v cc x1 x2 ain0 ain1 ain2 r st b le b he v bat v cco sclk i/o cs c ei c eol c eoh int gnd tssop (4.4mm) so (300 mils) ds1673 top view
ds1673 2 of 18 detailed description the microprocessor monitor circuitry of the ds1673 pr ovides three basic functions. first, a precision temperature-compensated reference and compar ator circuit monitors the status of v cc . when an out-of- tolerance condition occurs, an internal power-fail signal is generated which forces the reset to the active state. when v cc returns to an in-tolerance co ndition, the reset signals are ke pt in the active state for 250 ms to allow the power supply an d processor to stabili ze. the second microprocessor monitor function is pushbutton reset control. the ds1673 debounces a pus hbutton input and guarant ees an active reset pulse width of 250 ms. the third function is a watchdog timer. the ds 1673 has an internal timer that forces the reset signals to the active state if the st robe input is not driven low prior to watchdog timeout. the ds1673 also provides a 3-channel, 8-bit successive approximation analog-to-digital converter. the converter has an internal 2.55v (typical) reference voltage generated by an on-board band-gap circuit. the adc is monotonic (no missing codes) and has an internal analog filter to reduce high frequency noise. operation the block diagram in figure 1 shows the main elements of the ds1673. the following paragraphs describe the function of each pin. ds1673 block diagram figure 1
ds1673 3 of 18 pin description pin name function 1 v bat battery input for standard 3v lithium cell or other energy source 2 v cco external sram power supply output. this pin is internally connected to v cc when v cc is within nominal limits. however, during power-fail v cco is internally connected to the v bat pin. switchover occurs when v cc drops below v ccsw . 3 sclk serial clock input. used to synchronize data movement on the serial interface. 4 i/o data input/output. this pin is the bidirectional data pin for the 3-wire interface. 5 cs chip select. must be asserted high during a read or a write for communication over the 3-wire serial interface. cs has an internal 40k ? pulldown resistor. 6 cei ram chip-enable in. must be driven low to enable the external ram. 7 ceol ram chip-enable out low. active-low chip-enable output for low-order sram byte. 8 ceoh ram chip-enable out high. active-low chip-enable output for high-order sram byte. 9 int interrupt output. this pin is an active-high output that can be used as an interrupt input to a microprocessor. the int output remains high as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. the int pin operates when the ds1673 is powered by v cc or v bat . 10 gnd ground. dc power is provided to the device on this pin. 11 bhe byte high-enable input. this pin when driven low activates the ceoh output if cei is also driven low. 12 ble byte low-enable input. this pin when driven low activates the ceol output if cei is also driven low. 13 rst active-low reset. the rst pin functions as a microprocessor reset signal. this pin is driven low 1) when v cc is outside of nominal limits; 2) when the watchdog timer has timed out; 3) during the power-up reset period; and 4) in response to a pushbutton reset. the rst pin also functions as a pushbutton reset input. when the rst pin is driven low, the signal is debounced and timed such that a rst signal of at least 250ms is generated. this pin has an open-drain output with an internal 47k ? pullup resistor. 14, 15, 16 ain2, ain1, ain0 analog inputs. these pins are the three analog inputs for the 3-channel adc. 17, 18 x2, x1 connections for standard 32.768khz quartz crystal. for greatest accuracy, the ds1673 must be used with a crystal that has a specified load capacitance of 6pf. there is no need for external capacitors or resistors. note: x1 and x2 are very high- impedance nodes. it is recommended that they and the crystal be guard-ringed with ground and that high frequency signals be kept away from the crystal area. for more information on crystal selection and crystal layout considerations, refer to application note 58: crystal considerations with dallas real time clocks . the ds1673 does not function without a crystal. 19 v cc +3.0v or +5.0v input dc power 20 st active-low strobe input. the strobe input pin is used with the watchdog timer. if the st pin is not driven low within the watchdog time period, the rst pin is driven low.
ds1673 4 of 18 power-up/power-down considerations when v cc is applied to the ds1673 and reaches a level greater than v cctp (power-fail trip point), the device becomes fully accessible after t rpu (250ms typical). before t rpu elapses, all inputs are disabled. when v cc drops below v ccsw , the device is switched over to the v bat supply. during power-up, when v cc returns to an in-t olerance condition, the rst pin is kept in the active state for 250ms (typical) to allow the power supply and microprocessor to stabilize. address/command byte the command byte for the ds1673 is shown in figure 2. each data transfer is initiated by a command byte. bits 0 through 6 specify the address of the registers to be accessed. the msb (bit 7) is the read/write bit. this bit specifies whether the accesse d byte will be read or written. a read operation is selected if bit 7 is a 0 and a write operation is select ed if bit 7 is a one. the address map for the ds1673 is shown in figure 3. address/command byte figure 2
ds1673 5 of 18 ds1673 address map figure 3 clock, calendar, and alarm the time and calendar information is accessed by reading/ writing the appropriate register bytes. note that some bits are set to 0. these bits will always read 0 regardless of how they are written. also note that registers 0fh to 7fh are reserved. these registers will always read 0 regardless of how they are written. the contents of the time, calendar, and alarm regi sters are in the binary-coded decimal (bcd) format. the ds1673 can run in either 12-hour or 24-hour mode. bit 6 of the hours re gister is defined as the 12- or 24-hour mode select bit. when hig h, the 12-hour mode is selected. in the 12-hour mode, bit 5 is the am/pm bit with logic 1 being pm. in the 24-hour mode, bit 5 is the second 10-hour bit (20-23 hours). the ds1673 also contains a time of day alarm. the alarm registers are located in registers 07h to 0ah. bit 7 of each of the alarm re gisters are mask bits (see table 1). when all of the mask bits are logic 0, an alarm will occur once per week when the values stored in timekeeping registers 00h to 03h match the values stored in the time of day alarm registers. an alarm will be generated every day when mask bit of the day alarm register is set to 1. an alarm will be generated every hour when the day and hour alarm mask bits are set to 1. similarly, an alarm will be generated every minute when the day, hour, and minute alarm mask bits are set to 1. when day, hour, minute, and seconds alarm mask bits are set to 1, an alarm will occur every second.
ds1673 6 of 18 time of day alarm bits table 1 alarm register mask bits (bit 7) seconds minutes hours days description 1 1 1 1 alarm once per second. 0 1 1 1 alarm when seconds match. 0 0 1 1 alarm when minutes and seconds match. 0 0 0 1 alarm when hours, minutes and seconds match. 0 0 0 0 alarm when day, hour s, minutes and seconds match. special purpose registers the ds1673 has two additional registers (control regist er and status register) that control the rtc and interrupts. control register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 eosc wp ais1 ais0 0 0 0 aie eosc (enable oscillator). this bit, when set to logi c 0 will start the oscillator. when this bit is set to a logic 1, the oscillator is stopped and the ds1673 is pl aced into a low-power standby mode with a current drain of less than 200na when in battery-backup mode. when the ds1673 is powered by v cc , the oscillator is always on rega rdless of the status of the eosc bit; however, the rtc is incremented only when eosc is a logic 0. wp (write protect). before any write operation to the rtc or a ny other registers, this bit must be logic 0. when high, the write protect bit preven ts a write operation to any register. ais0-ais1 (analog input select). these 2 bits are used to determin e the analog input for the analog-to- digital conversion. table 2 lists the specific analog i nput that is selected by these 2 bits. aie (alarm interrupt enable). when set to a logic 1, this bit pe rmits the interrupt request flag (irqf) bit in the status register to assert int. when the ai e bit is set to logic 0, the irqf bit does not initiate the int signal. analog input selection table 2 ais1 ais0 analog input 0 0 none 0 1 ain0 1 0 ain1 1 1 ain2
ds1673 7 of 18 status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cu lobat 0 0 0 0 0 irqf cu (conversion update in progress). when this bit is a 1, an update to the adc register (register 0eh) will occur within 488 ? s. when this bit is a 0, an update to the adc register will not occur for at least 244 ? s. lobat (low battery flag). this bit reflects the status of th e backup power source connected to the v bat pin. when v bat is greater than 2.5v, lobat is set to a logic 0. when v bat is less than 2.3v, lobat is set to a logic 1. irqf (interrupt request flag). a logic 1 in the interr upt request flag bit indicates that the current time has matched the time of day alarm registers. if the aie bit is also a logic 1, the int pin will go high. irqf is cleared by reading or writ ing to any of the alarm registers. power-up default states these bits are set to a one upon initial power-up: eosc , td1 and td0. these bits are cleared upon initial power-up: wp, ais1, and ais0. nonvolatile sram controller the ds1673 provides automatic backup and write pr otection for external sram. this function is provided by gating the chip enable signals and by providing a cons tant power supply through the v cco pin. the ds1673 was specifically designed with the intel 80186 and 386ex microprocessors in mind. as such, the ds1673 has the capability to provide access to the external sram in either byte-wide or word- wide format. this capability is provided by the chip enable scheme. three input signals and two output signals are used for enabling the external sram(s) (see figure 4). cei (chip enable in), bhe (byte high enable), and ble (byte low enable) are used for enabling ei ther one or two external srams through the ceol (chip enable low) and the ceoh (chip enable high) outputs. ta ble 3 illustrates the function of these pins. the ds1673 nonvolatilizes the extern al sram(s) by write-protecting the sram(s) and by providing a back-up power supply in the absence of v cc . when v cc falls below v pf , access to the external sram(s) are prohibited by forcing ceol and ceoh high regardless of the level of cei , ble , and bhe . upon power-up, access is prohibited until the end of t rpu . external sram chip enable table 3 cei bhe ble ceol ceoh function 0 0 0 0 0 word transfer 0 0 1 1 0 byte transfer in uppe r half of data bus (d15-d8) 0 1 0 0 1 byte transfer in lo wer half of data bus (d7-d0) 0 1 1 1 1 external srams disabled 1 x x 1 1 external srams disabled
ds1673 8 of 18 external sram interface (word-wide) to the ds1673 figure 4 microprocessor monitor the ds1673 monitors three vital conditions for a mi croprocessor: power supply, software execution, and external override. first, a precision temperature-compensated reference and comparator circuit monitors the status of v cc . when an out-of-tolerance condition occurs, an intern al power-fail signal is ge nerated which forces the rst pin to the active state, thus warning a processo r-based system of impendi ng power failure. when v cc returns to an in-tolerance condition upon power-up, th e reset signal is kept in the active state for 250ms (typical) to allow the power supply and microprocessor to stabili ze. note, however, that if the eosc bit is set to a logic 1 (to disa ble the oscillator duri ng battery-backup mode), th e reset signal will be kept in an active state for 250 ms plus the start-up time of the oscillator. the second monitoring function is push-button reset control. the ds1673 provides for a pushbutton switch to be connected to the rst output pin. when the ds1673 is not in a reset cycle, it continuously monitors the rst signal for a low going edge. if an edge is detected, the ds1673 will debounce the switch by pulling the rst line low. after the internal 250ms ti mer has expired, the ds1673 will continue to monitor the rst line. if the line is still lo w, the ds1673 will continue to monitor the line looking for a rising edge. upon detecting rel ease, the ds1673 will force the rst line low and hold it low for 250ms. the third microprocessor monitoring function provided by the ds1673 is a watchdog timer. the watchdog timer function forces rst to the active state when the st input is not stimulated within the predetermined time period. the time period is set by th e time delay (td) bits in the watchdog register. the time delay can be set to 250ms, 500ms, or 1000ms (see figure 5). if td0 and td1 are both set to zero, the watchdog timer is disabled . when enabled, the watchdog timer starts timing out from the set time period as soon as rst is inactive. the default setting is for the watchdog timer to be enabled with 1000ms time delay. if a high-to-l ow transition occurs on the st input pin prior to time-out, the watchdog timer is reset and begins to ti me-out again. if the watchdog timer is allowed to tim e-out, then the rst signal is driven to the active state for 250ms (typical). the st input can be derive d from microprocessor address signals, data signals, an d/or control signals. to guarantee that the watchdog timer does not time- out, a high-to-low transition must occu r at or less than the minimum period.
ds1673 9 of 18 watchdog time-out control figure 5 watchdog register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 0 td1 td0 watchdog register td1 td0 watchdog time-out 0 0 watchdog disabled 0 1 250 ms 1 0 500 ms 1 1 1000 ms analog-to-digital converter the ds1673 provides a 3-channel, 8- bit analog-to-digital converter. the adc reference voltage (2.55v typical) is derived from an on-chip band-gap ci rcuit. three multiplexed analog inputs are provided through the ain0, ain1, and ain2 pins. the adc is monotonic (no missing codes) and uses a successive approximation technique to convert the analog signal into a digital code. an a/d conversion is the process of assigning a digital code to an analog input voltage. this code represents the input value as a frac tion of the full-scale voltage (fsv) range. thus, the fsv range is then divided by the adc into 256 codes (8 bits). the fsv range is bounded by an upper limit equal to the reference voltage and the lower limit, which is ground. the ds1673 has a fsv of 2.55v (typical) that provides a resolution of 10mv. an i nput voltage equal to the reference voltage converts to ffh while an input voltage equal to ground converts to 00h. the relative linear ity of the adc is ? 0.5 lsb. the a/d converter selects from on e of three different analog inputs (ain0?ain2). the input that is selected is determined by the analog input select (a is) bits in the control register. table 2 lists the specific analog input that is selected by these 2 bits. note also th at the converter can be turned off by these bits to reduce power. when the adc is turned on by setting ais0 and ais1 to any value other than 0,0 the analog input voltage is converted a nd written to the adc register within 488 ? s. an internal analog filter at the input reduces high frequency noise. subsequent updates occur appr oximately every 10ms. if ais0 and/or ais1 are changed, updates w ill occur at the next 10 ms conversion time. the conversion update in progress (cu) bit in the st atus register indicates wh en the adc register can be read. when this bit is a 1, an update to the adc register will occur within 488 ? s maximum. however, when this bit is 0 an update will not occur for at least 244 ? s. the cu bit should be polled before reading the adc register to insure that th e contents are stable during a read cycle. once a read cycle to the adc register has been started, the ds1673 will not update that register until the read cycle has been completed. it should also be mentioned that taking cs low will abort the read cycle and will allow the adc register to be updated. figure 6 illustrates the timing of the cu bit relative to an instru ction to begin conversion and the completion of that conversion.
ds1673 10 of 18 cu bit timing figure 6 3-wire serial interface communication with the ds1673 is accomplished through a simple 3-wire interface consisting of the chip select (cs), seri al clock (sclk) and i nput/output (i/o) pins. all data transfers are initiated by dr iving the cs input high. the cs input serves two functions. first, cs turns on the control logic, which allows access to the shift register for the address/command sequence. second, the cs signal provides a method of terminating either single byte or multiple byte (burst) data transfer. a clock cycle is a sequence of a rising edge followed by a fallin g edge. for data input, data must be valid during the rising edge of th e clock and data bits are output on th e falling edge of the clock. if the cs input goes low, all data transfer terminates and the i/o pin goes to a high impedance state. address and data bytes are always shifted lsb first into the i/o pin. any transaction requires the address/command byte to specify a read or write to a specific register followed by 1 or more bytes of data. the address byte is always th e first byte entered after cs is driven high. the most significant bit ( rd /wr) of this byte determines if a read or write will take place. if this bit is 0, one or more read cycles will occur. if this bit is 1, one or more write cycles will occur. data transfers can occur 1 byte at a time or in multiple byte burst mode. after cs is driven high an address is written to the ds1673. after the address, 1 or more data bytes can be read or written. for a single-byte transfer 1 byte is read or written and th en cs is driven low. for a multiple-byte transfer, multiple bytes can be read or written to the ds1673 after the addres s has been written. each read or write cycle causes the register address to automatically in crement. incrementing conti nues until the device is disabled. after accessing register 0eh, the address wraps to 00h. data transfer for single-byte transfer and multiple-byt e burst transfer is illustrated in figures 7 and 8.
ds1673 11 of 18 single-byte data transfer figure 7 multiple-byte burst transfer figure 8
ds1673 12 of 18 absolute maxi mum ratings voltage on any pin relative to ground????????????????????.-0.3v to +7.0v operating temperature???????????????????????????..0c to +70c storage temperature???????????????????????????.-55c to +125c soldering temperature?????????????????????..see j-std-020 specification this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in t he operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. recommended dc operating conditions (t a = 0 ? c to +70 ? c) parameter symbol min typ max units notes 5.0v 4.5 5.0 5.5 power supply voltage 3.0v v cc 2.7 3.0 3.3 v 1 input logic 1 v ih 2.0 v cc +0.3 v 1 input logic 0 v il -0.3 +0.8 v 1 battery voltage v bat 2.5 3.7 v 1 dc electrical characteristics (v cc = 5.0v 10%, t a = 0 ? c to +70 ? c.) parameter symbol min typ max units notes input leakage i li -1 +1 ? a cs leakage i lo 150 ? a 7 logic 1 output (i out = -0.4ma) v oh 2.4 v 2 logic 0 output (i out = 1.5ma) v ol 0.4 v 3 active supply current (cs = v cc - 0.2) i cca 1.5 2.0 ma 4 a/d converter current i adc 500 ? a 5 standby current (cs = v il ) i ccs 300 ? a 6 battery current (oscillator on) i bat1 300 500 na battery current (oscillator off) i bat2 200 na internal rst pullup resistor r p 35 47 60 k ? v cc trip point v cctp 4.25 4.35 4.50 v v cc switchover v ccsw 2.60 2.70 2.80 v 12 a/d reference voltage v adc 2.47 2.55 2.63 v pushbutton detect pb dv 0.8 2.0 v pushbutton release pb rd 0.3 0.8 v output voltage v cco v cc -0.3 v 11 v cco output current (source = v cc ) i cco1 150 ma 13 v cco output current (source = v bat ) i cco2 150 ? a 14
ds1673 13 of 18 dc electrical characteristics (v cc = 3.0v 10%, t a = 0 ? c to +70 ? c.) parameter symbol min typ max units notes input leakage i li -1 +1 ? a cs leakage i lo 150 ? a 7 logic 1 output (i out =-0.4ma) v oh 2.4 v 2 logic 0 output (i out = 1.5ma) v ol 0.4 v 3 active supply current (cs = v cc - 0.2) i cca 0.75 1.0 ma 4 adc current i adc 200 ? a 5 standby current (cs = v il ) i ccs 100 ? a 6 battery current (oscillator on) i bat1 300 500 na battery standby current (oscillator off) i bat2 200 na internal rst pullup resistor r p 35 47 60 k ? v cc trip point v cctp 2.5 2.6 2.7 v v cc switchover v ccsw 2.30 2.40 2.50 v 12 a/d reference voltage v adc 2.47 2.55 2.63 v pushbutton detect pb dv 0.8 2.0 v pushbutton release pb rd 0.3 0.8 v output voltage v cco v cc -0.3 v 11 v cco output current (source = v cc ) i cco1 80 ma 13 v cco output current (source = v bat ) i cco2 100 ? a 14 capacitance (t a = +25 ? c) parameter symbol min typ max units notes input capacitance c i 10 pf i/o capacitance c i/o 15 pf crystal capacitance c x 6 pf
ds1673 14 of 18 ac electrical characteristics (v cc = 5.0v 10%, t a = 0 ? c to 70 ? c.) parameter symbol min typ max units notes data to clock setup t dc 50 ns 8 clk to data hold t cdh 70 ns 8 clk to data delay t cdd 200 ns 8, 9, 10 clk to low time t cl 250 ns 8 clk to high time t ch 250 ns 8 clk frequency t clk 2.0 mhz 8 clk rise and fall t r , t f 500 ns cs to clk setup t cc 1 ? s 8 clk to cs hold t cch 60 ns 8 cs inactive time t cwh 1 ? s 8 cs to i/o high-z t cdz 70 ns 8 v cc slew rate (4.5v to 2.3v) t f 1 ms v cc slew rate (2.3v to 4.5v) t r 0 ns v cc detect to rst (v cc falling) t rpd 100 ns reset active time t rst 250 ms 15 pushbutton debounce pb db 250 ms 15 v cc detect to rst (v cc rising) t rpu 250 ms 15, 16 st pulse width t st 20 ns chip enable propagation delay to external sram t ced 8 15 ns nominal voltage to v cc switchover fall time t fb 200 ? s
ds1673 15 of 18 ac electrical characteristics (v cc = 3.0v 10%, t a = 0 ? c to +70 ? c.) parameter symbol min typ max units notes data to clock setup t dc 150 ns 8 clk to data hold t cdh 210 ns 8 clk to data delay t cdd 600 ns 8, 9, 10 clk to low time t cl 750 ns 8 clk to high time t ch 750 ns 8 clk frequency t clk 0.667 mhz 8 clk rise and fall t r , t f 1500 ns cs to clk setup t cc 3 ? s 8 clk to cs hold t cch 180 ns 8 cs inactive time t cwh 3 ? s 8 cs to i/o high-z t cdz 210 ns 8 v cc slew rate (2.7v to 2.3v) t f 300 ? s v cc slew rate (2.3v to 2.7v) t r 0 ns v cc detect to rst (v cc falling) t rpd 200 ns reset active time t rst 250 ms 15 pushbutton debounce pb db 250 ms 15 v cc detect to rst (v cc rising) t rpu 250 ms 15, 16 st pulse width t st 40 ns chip enable propagation delay to external sram t ced 8 25 ns nominal voltage to v cc switchover fall time t fb 300 ? s
ds1673 16 of 18 timing diagram: read data figure 9 timing diagram: write data figure 10
ds1673 17 of 18 pushbutton reset figure 11 power-up figure 12 power-down figure 13
ds1673 18 of 18 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxi m/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2005 maxim integrated products the maxim logo is a registered trademark of maxim integrated produ cts, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. notes: 1. all voltages are referenced to ground. 2. logic 1 voltages are specified at v cc = 3.0v, v oh = v cc for capacitive loads. excludes rst pin 3. logic 0 voltages are specified at v cc = 3.0v, v ol = gnd for capacitive loads. 4. i cca is specified with outputs open, cs set to a logic 1, sclk = 500khz, oscillator enabled, and d/a converter enabled. 5. i adc is specified with cs, v cco open and i/o, sclk at logic 0. adc is enabled. 6. i ccs is specified with cs, v cco open and i/o, sclk at logic 0. adc is disabled. 7. cs has a 40k ? pulldown resistor to ground. 8. measured at v ih = 2.0v or v il = 0.8v and 10ns maximum rise and fall time. 9. measured at v oh = 2.4v or v ol = 0.4v. 10. load capacitance = 25pf. 11. i cco = 100ma, v cc > v cctp . 12. v cco switchover from v cc to v bat occurs when v cc drops below the lower of v ccsw and v bat . 13. current from v cc input pin to v cco output pin. 14. current from v bat input pin to v cco output pin. 15. time base is generated by very accurate crystal osc illator. accuracy of this time period is based on the crystal that is used. a typical crystal with a specified load capacitance of 6pf will provide an accuracy within 100ppm over the 0c to +70c temperature range. 16. if the eosc bit in the control register is set to a logic 1, t rpu is equal to 250ms plus the startup time of the crystal oscillator. package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 20 tssop u20+1 21-0066 20 so w20+3 21-0042

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